1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which allows increase in degree of integration and capacity and a method for fabricating the nonvolatile semiconductor memory device, and also relates to a semiconductor switching device.
2. Description of the Prior Art
A ferroelectric memory (FeRAM), which is one of nonvolatile memories, uses a polarization hysteresis of a ferroelectric material for memory retaining. In such a ferroelectric memory, inversion of polarization can be repeated for many times at low voltage and high speed, and thus a ferroelectric memory is considered excellent, compared to a flash memory, in the point that it can be operated with low power consumption, at high speed and with high reliability.
There are largely two types of ferroelectric memories: a capacitor type shown in FIG. 26A (see, for example, Japanese Laid-Open Publication No. 9-116107 and Japanese Laid-Open Publication No. 2000-156089); and an FET (Field Effect Transistor) type having a structure in which a gate insulation film of a metal-oxide-semiconductor (MOS) transistor shown in FIG. 26B is replaced with a ferroelectric film (see, for example, U.S. Pat. No. 6,744,087).
A capacitor type ferroelectric memory has a similar structure to that of a dynamic random access memory (DRAM) in which charges are held in a ferroelectric capacitor and a state of information is judged to be 0 or 1 according to the polarization direction of a ferroelectric material.
With this structure, as shown in FIG. 27A, when capacitors serving as function units are connected to one another at each cross point and thereby are formed into array type elements, a memory size can be reduced to 4F2 in terms of design rule. Herein, F is a size according to a fine design rule. A relative occupied area can be indicated using F.
However, practically, a capacitor type ferroelectric memory is not suitable for reduction in size because when a capacitor area is reduced, the amount of charges (ΔQ) that can be held therein is reduced and, as shown in FIG. 27B, finally becomes lower than a limit level (about 100 fC) for reading by a sense amplifier. Thus, it becomes difficult to judge a state of information to be 0 or 1. The amount of a remnant polarization (Pr) for a typical ferroelectric material is about 10-50 μC/cm at best. Thus, when a CMOS process is reduced and a gate length of a MOS transistor becomes a process node of 0.1 μm or less, a practical minimum cell size is about 20 F2 at best.
On the other hand, in a FET type ferroelectric memory, information is read by detecting a conduction state of a channel, which varies depending on a polarization direction of a ferroelectric layer. To satisfy the scaling law, only a small amount of polarization charges per unit area is required. Therefore, a FET type ferroelectric memory is suitable for reduction in size, compared to a capacitor type memory.
However, when a FET type memory is operated as a memory, an arbitrary memory cell has to be selected from memory cells arranged in arrays in the FET type memory and thus a switching transistor for selecting a memory cell is needed. Even though a structure (stacking structure) in which a transistor for memory cell selection and a ferroelectric transistor for memory retaining are stacked is adopted to reduce the size of memory cells, a minimum size of the ferroelectric transistor with the selection transistor is about 12 F2 at best and is still larger than an ideal size, i.e., 4 F2 for a ferroelectric memory with a reduced size.
As described above, a ferroelectric memory exhibits excellent properties such as low power consumption, high speed operation and high reliability, and at the same time it has a problem that it is difficult to reduce its size. For this reason, a memory capacity of only megabits at largest has been achieved by now. Therefore, in actual cases, application of ferroelectric memories is limited to an IC tag, a smart card and the like.
On the other hand, a flash memory can be fabricated to have a minimum cell size of 4F2 and thus a capacity of gigabits has been achieved. Therefore, flash memories have been widely used for large capacity application such as a picture card for digital cameras, USB memory sticks and the like.
In recent years, more and more nonvolatile memories using resistance modulation are under research and development. A resistance modulation element reads resistance change and is scalable, and thus reduction in size of a memory device can be expected. Examples of such nonvolatile memories are a magnetic memory (MRAM; Magnetoresistive Random Access Memory) using change in magnetic resistance according to a direction of spinning of a magnetic body (see, for example, Japanese Laid-Open Publication No. 2003-282837), a resistance change memory (ReRAM; Resistive Random Access Memory) using the colossal electro-resistance (CER) effect of a strongly-correlated material (see, for example, Japanese Laid-Open Publication No. 2005-317787), a phase change memory (PRAM; Phase Change Random Access Memory) using resistance change according to phase transition of chalcogenide compound (see, for example, Japanese-Laid-Open Publication No. 2004-031953) and the like. If array type elements are formed so as to be connected to one another at each cross point, as shown in FIG. 27A, using a resistance change layer as a function unit, a constant resistance change (ΔR=RH/RL), which is not dependent on a cell area, is achieved, and thus a minimum cell size of 4F2 can be realized.